Flip-flop circuits are used in semiconductor devices to maintain a binary state indefinitely until directed by an input signal to switch states. A variation of the basic flip-flop circuit, the clocked flip-flop circuit responds to input levels in response to a clock signal. Used in this manner, the clocked flip-flop circuit acts as a sampling device which only reads the information off of its input line when directed to do so by the clocking circuit. After reading the information, the circuit stores the information and outputs it on the output line. In all other instances of time, the circuit will not respond to input signals and will remain unchanged during variations of signal states in the input line.
Despite their usefulness, typical flip-flops have many shortcomings. One such typical flip-flop is the CMOS static flip-flop. The CMOS static flip-flop is relatively slow and occupies a relatively large amount of space. It has a long setup time requirement and has large input loads. Finally, the input node is sensitive to power line noise.
Other typical flip-flops have other disadvantages. One such flip-flop is the CMOS dynamic flip-flop. It loses data when the clock is stopped. In addition, it does not perform well under low frequency operation. Finally, it experiences body effect problems causing difficulties during low voltage operation.
Thus, what is needed is a flip-flop circuit that is fast, occupies a small area, possesses a short setup time, has a small input load, maintains data when the clock is stopped, possesses safety for lower frequency operation, overcomes the body effect problem and has decreased sensitivity to power line noise.